The manufacture of integrated circuits (IC), semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto-electronic devices, magneto-optic devices, packaged devices, and the like entails the integration and sequencing of many unit processing steps. As an example, IC manufacturing typically includes a series of processing steps such as cleaning, surface preparation, deposition, lithography, patterning, etching, planarization, implantation, thermal annealing, and other related unit processing steps. The precise sequencing and integration of the unit processing steps enables the formation of functional devices meeting desired performance metrics such as speed, power consumption, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, and U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006 which are all herein incorporated by reference.
Typically, during the discovery, optimization and qualification of each unit process, it is desirable to utilize sample material in an efficient manner. Therefore, it is common to divide substrate material into smaller units known as coupons. As used herein, coupon will be understood to mean a smaller section of a substrate. The coupon will be understood to have all of the properties and functionality as the substrate. For example, if the substrate is a semiconductor wafer with a plurality of devices thereon, then a coupon is understood to be a section of the wafer and each coupon is understood to also contain a plurality of devices.
In an R&D environment, the coupons are generally tested individually at a probe station to determine the electrical properties of the materials or the performance of the devices. Since the coupons are non-standard sections of the wafer, the testing requires manual set-up and calibration at the probe station. Once the reference coordinates of the coupon have been determined and a relative offset to the test pads of the target devices, the probe station can usually complete the testing of all of the devices or test regions of the coupon automatically. However, this set-up procedure must be repeated for each coupon.
The electrical tests for a typical coupon can vary in time and can range from a few minutes to many hours depending on the number of devices, the number of tests to be performed, etc. This requires that a technician be available when the testing of one coupon is completed so that the next coupon can be mounted, calibrated, and the testing initiated. Since the test time varies, it is common for the probe station to be idle and waiting for the technician to start the sequence for the next coupon. Alternatively, it is common for the technician to be idle and waiting for the probe station to complete the testing so that the sequence for the next coupon can be started. In both cases, valuable resources are being used in a sub-optimal manner leading to increased costs and longer development times.
Therefore, there is a need to develop methods for testing multiple coupons that increases the utilization of the probe station resources and increases the utilization of the technician's time. There is a need for methods that allow the probe station to operate autonomously after a set-up and calibration procedure so that technician intervention is not required.